ST7232A
16-BIT TIMER
(Cont鈥檇)
10.3.4 Low Power Modes
Mode
WAIT
Description
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with 鈥渆xit from HALT mode鈥?capability or from the counter
reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-
ly, when the MCU is woken up by an interrupt with 鈥渆xit from HALT mode鈥?capability, the ICFi bit is set, and
the counter value present when exiting from HALT mode is captured into the ICiR register.
HALT
10.3.5 Interrupts
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Event
Flag
ICF1
ICF2
OCF1
OCF2
TOF
Enable
Control
Bit
ICIE
OCIE
TOIE
Exit
from
Wait
Yes
Yes
Yes
Yes
Yes
Exit
from
Halt
No
No
No
No
No
Note:
The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
10.3.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse Mode
PWM Mode
Input Capture 1
Yes
Yes
No
No
TIMER RESOURCES
Input Capture 2
Output Compare 1 Output Compare 2
2)
Yes
Yes
Yes
Yes
Yes
Yes
1)
No
Partially
2)
Not Recommended
Not Recommended
3)
No
No
1) See note 4 in
Section 10.3.3.5 One Pulse Mode
2) See note 5 and 6 in
Section 10.3.3.5 One Pulse Mode
3) See note 4 in
Section 10.3.3.6 Pulse Width Modulation Mode
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