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ST7232AK1B1 Datasheet

  • ST7232AK1B1

  • 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFA...

  • 1290.53KB

  • 154页

  • STMICROELECTRONICS   STMICROELECTRONICS

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ST7232A
SERIAL PERIPHERAL INTERFACE
(Cont鈥檇)
10.4.5.4 Single Master Systems
A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see
Figure 49).
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note:
To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Figure 49. Single Master / Multiple Slave Configuration
SS
SCK
Slave
MCU
MOSI MISO
SCK
Slave
MCU
SS
SCK
Slave
MCU
SS
SCK
Slave
MCU
SS
MOSI MISO
MOSI MISO
MOSI MISO
MOSI MISO
SCK
Master
MCU
5V
SS
Ports
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