ST7232A
SERIAL COMMUNICATIONS INTERFACE
(Cont鈥檇)
10.5.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in
Figure 50.
It contains 6 dedicated reg-
isters:
鈥?Two control registers (SCICR1 & SCICR2)
鈥?A status register (SCISR)
鈥?A baud rate register (SCIBRR)
鈥?An extended prescaler receiver register (SCIER-
PR)
鈥?An extended prescaler transmitter register (SCI-
ETPR)
Refer to the register descriptions in
Section
10.5.7for
the definitions of each bit.
10.5.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see
Figure 50).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of 鈥?鈥漵 followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving 鈥?鈥漵
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra 鈥?鈥?bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Figure 51. Word Length Programming
9-bit Word length (M bit is set)
Data Frame
Start
Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Possible
Parity
Bit
Bit8
Next Data Frame
Next
Stop Start
Bit
Bit
Start
Bit
Idle Frame
Break Frame
Extra
鈥?鈥?/div>
Start
Bit
8-bit Word length (M bit is reset)
Data Frame
Start
Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Possible
Parity
Bit
Bit7
Stop
Bit
Next Data Frame
Next
Start
Bit
Start
Bit
Extra Start
Bit
鈥?鈥?/div>
Idle Frame
Break Frame
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