CYM1464
Switching Characteristics
Over the Operating Range
[3]
1464-20
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
t
WC
t
SCS
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
CS HIGH to High Z
[4]
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
[4]
0
0
5
0
20
15
15
3
5
15
12
2
0
15
[3]
1464-22
Min.
22
Max.
1464-25
Min.
25
Max.
1464-30
Min.
30
Max.
Unit
ns
30
5
30
15
0
0
10
0
30
25
25
3
5
20
15
2
0
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
ns
Description
Min.
20
Max.
20
5
20
13
0
10
15
0
5
0
22
17
15
3
5
15
12
2
0
5
22
5
22
13
0
10
15
0
5
0
25
20
20
3
5
15
15
2
0
15
25
25
15
10
15
WRITE CYCLE
[5]
15
Switching Characteristics
Over the Operating Range
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACS
t
DOE
t
LZOE
t
HZOE
t
LZCS
t
HZCS
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
CS HIGH to High Z
[4]
Description
1464-35
Min.
35
35
5
35
20
0
0
10
0
20
15
0
0
5
Max.
1464-45
Min.
45
45
5
45
25
0
15
20
0
Max.
1464-55
Min.
55
55
55
30
15
20
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0
10
0
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
4. t
HZCS
and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured
卤
500 mV from steady-state voltage.
5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05272 Rev. **
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