ISL90727
Operating Specifications
SYMBOL
I
CC1
I
SB
I
ComLkg
t
DCP
(Note 10)
V
CC
Ramp
t
D
PARAMETER
V
CC
supply current
(Volatile write/read)
V
CC
current (standby)
Common-Mode Leakage
DCP wiper response time
V
CC
ramp rate
Power-up delay
V
CC
above Vpor, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby
state
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for I
2
C, Active,
Read and Volatile Write States only)
V
CC
= +5.5V, I
2
C Interface in Standby State
Voltage at SDA pin to GND or V
CC
SCL falling edge of last bit of DCP Data Byte to
wiper change
0.2
3
500
MIN
TYP
(Note 1)
MAX
200
500
3
UNIT
碌A
nA
碌A
ns
V/ms
ms
SERIAL INTERFACE SPECIFICATIONS
V
IL
V
IH
Hysteresis
V
OL
Cpin (Note 12)
f
SCL
t
IN
t
AA
t
BUF
SDA, and SCL input buffer LOW
voltage
SDA, and SCL input buffer HIGH
voltage
SDA and SCL input buffer
hysteresis
SDA output buffer LOW voltage,
sinking 4mA
SDA, and SCL pin capacitance
SCL frequency
Pulse width suppression time at
SDA and SCL inputs
SCL falling edge to SDA output
data valid
Time the bus must be free before
the start of a new transmission
Clock LOW time
Clock HIGH time
START condition setup time
START condition hold time
Input data setup time
Input data hold time
STOP condition setup time
STOP condition hold time for
read, or volatile only write
Output data hold time
SDA and SCL rise time
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window.
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
From SCL falling edge crossing 30% of V
CC
,
until SDA enters the 30% to 70% of V
CC
window.
From 30% to 70% of V
CC
1300
-0.3
0.7*
V
CC
0.05*
V
CC
0
0.4
10
400
50
900
0.3*
V
CC
V
CC
+
0.3
V
V
V
V
pF
kHz
ns
ns
ns
t
LOW
t
HIGH
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HD:STO
t
DH
t
R
(Note 12)
1300
600
600
600
100
0
600
600
0
20 +
0.1 * Cb
250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
FN8247.1
August 1, 2005
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