MSM6222 Datasheet

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隆 Semiconductor

MSM6222B-xx

Data Bus Connected with CPU

The data bus connected with CPU is available either once for 8 bits or twice for 4 bits. This

allows the MSM6222B-xx to be interfaced with either an 8-bit or 4-bit CPU.

(1) When the interface data length is 8 bits

Data buses DB

0

to DB

7

(8 buses) are all used and data input/output is carried out in

one step.

(2) When the interface data length is 4 bits

The 8-bit data input/output is carried out in two steps by using only high-order 4 bits

of data buses DB

4

to DB

7

(4 buses)

The first time data input/output is made for 4-high order bits (DB

4

to DB

7

when the

interfaces data length is 8 bits) and the second time data input/output is made for low-

order 4 bits (DB

0

to DB

3

when the interface data length is 8 bits). Even when the data

input/output can be completely made through high-order 4 bits, be sure to make

another input/output of low-order 4 bits. (Example: Busy flag Read).

Since the data input/output is carried out in two steps but as one execution, no normal

data transfer is executed from the next input/output if accessed only once.

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