您的位置：维库电子市场网 > Datasheet > PC28F128J3A-110

PC28F128J3A-110 Datasheet

  • PC28F128J3A-110

  • Intel StrataFlash Memory (J3)

  • 909.85KB

  • 72页

  • INTEL

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

256-Mbit J3 (x8/x16)
7.2
Table 9.
Write Operations
Write Operations
Versions
Valid for All
Speeds
Parameter
RP# High Recovery to WE# (CE
X
) Going Low
CE
X
(WE#) Low to WE# (CE
X
) Going Low
Write Pulse Width
Data Setup to WE# (CE
X
) Going High
Address Setup to WE# (CE
X
) Going High
CE
X
(WE#) Hold from WE# (CE
X
) High
Data Hold from WE# (CE
X
) High
Address Hold from WE# (CE
X
) High
Write Pulse Width High
V
PEN
Setup to WE# (CE
X
) Going High
Write Recovery before Read
WE# (CE
X
) High to STS Going Low
V
PEN
Hold from Valid SRD, STS Going High
0
Min
1
0
70
50
55
0
0
0
30
0
35
500
Max
碌s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,4
1,2,4
1,2,5
1,2,5
1,2,
1,2,
1,2,
1,2,6
1,2,3
1,2,7
1,2,8
1,2,3,8,9
Unit
Notes
#
W1
W2
W3
W4
W5
W6
W7
W8
W9
W11
W12
W13
W15
Symbol
t
PHWL
(t
PHEL
)
t
ELWL
(t
WLEL
)
t
WP
t
DVWH
(t
DVEH
)
t
AVWH
(t
AVEH
)
t
WHEH
(t
EHWH
)
t
WHDX
(t
EHDX
)
t
WHAX
(t
EHAX
)
t
WPH
t
VPWH
(t
VPEH
)
t
WHGL
(t
EHGL
)
t
WHRL
(t
EHRL
)
t
QVVL
NOTES:
CE
X
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
X
high is defined at the first edge of CE0, CE1,
or CE2 that disables the device (see
Table 13).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to
AC Characteristics鈥揜ead-Only Operations.
2. A write operation can be initiated and terminated with either CE
X
or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (t
WP
) is defined from CE
X
or WE# going low (whichever goes low last) to CE
X
or WE# going
high (whichever goes high first). Hence, t
WP
= t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
5. Refer to
Table 14
for valid A
IN
and D
IN
for block erase, program, or lock-bit configuration.
6. Write pulse width high (t
WPH
) is defined from CE
X
or WE# going high (whichever goes high first) to CE
X
or WE#
going low (whichever goes low first). Hence, t
WPH
= t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
.
7. For array access, t
AVQV
is required in addition to t
WHGL
for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY# default mode.
9. V
PEN
should be held at V
PENH
until determination of block erase, program, or lock-bit configuration success
(SR[1,3,4:5] = 0).
26
Datasheet

PC28F128J3A-110相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！