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S25FL004D0LNAI013 Datasheet

  • S25FL004D0LNAI013

  • 4 Megabit CMOS 3.0 Volt Flash Memory with 50 Mhz SPI Bus Int...

  • 792.53KB

  • 36页

  • SPANSION   SPANSION

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A d v a n c e
I n f o r m a t i o n
CS#
0
1
2
3
4
5
6
7
SCK
Instruction
SI
Figure 13.
Bulk Erase (BE) Instruction Sequence
Deep Power Down (DP)
The Deep Power Down (DP) instruction puts the device in the lowest current
mode of 1
碌A
typical.
It is recommended that the standard Standby mode be used for the lowest power
current draw, as well as the Deep Power Down (DP) as an extra software protec-
tion mechanism when this device is not in active use. In this mode, the device
ignores all Write, Program and Erase instructions. Chip Select (CS#) must be
driven Low for the entire duration of the sequence.
The Deep Power Down (DP) instruction is entered by driving Chip Select (CS#)
Low, followed by the instruction code on Serial Data Input (SI). Chip Select (CS#)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Figure 14.
Driving Chip Select (CS#) High after the eighth bit of the instruction code has
been latched puts the device in Deep Power Down mode. The Deep Power Down
mode can only be entered by executing the Deep Power Down (DP) instruction to
reduce the standby current (from I
SB
to I
DP
as specified in Table
6).
As soon as
Chip Select (CS#) is driven high, it requires a delay of t
DP
currently in progress
before Deep Power Down mode is entered.
Once the device has entered the Deep Power Down mode, all instructions are ig-
nored except the Release from Deep Power Down (RES) and Read Electronic
Signature. This releases the device from the Deep Power Down mode. The Re-
lease from Deep Power Down and Read Electronic Signature (RES) instruction
also allows the Electronic Signature of the device to be output on Serial Data Out-
put (SO).
The Deep Power Down mode automatically stops at Power-down, and the device
always powers up in the Standby mode.
Any Deep Power Down (DP) instruction, while an Erase, Program or WRSR cycle
is in progress, is rejected without having any effect on the cycle in progress.
22
S25FL Family (Serial Peripheral Interface) S25FL004D
S25FL004D_00A0 June 28, 2004

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