维库电子市场网-十六年专注打造电子元器件采购网

编译时说missing source什么意思怎么改

e ieee.std_logic_unsigned.all;entity time is port(clk:in std_ulogic;data:out std_ulogic_vector(3 downto 0);control:out std_ulogic_vector(2 downto 0));end time;architecture rtl of time issignal sec,min,hour:std_logic_vector(3 downto 0);signal sec10,min10,hour10:std_logic_vector(2 downto 0);signal qs:std_logic_vector(2 downto 0);signal data_out:std_ulogic_vector(3 downto 0);signal control_out:std_ulogic_vector(2 downto 0);beginprocess(clk)variable pos_sel,count_sel:integer;variable q1,q3,q5:integer r