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AD9511 Datasheet

  • AD9511

  • 1.2 GHz Clock Distribution IC, PLL Core,Dividers, Delay Adju...

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1.2 GHz Clock Distribution IC, PLL Core,
Dividers, Delay Adjust, Five Outputs
AD9511
FEATURES
Low phase noise phase-locked loop core
Reference input frequencies to 250 MHz
Programmable dual-modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCP
S
) extends tuning range
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Space-saving 48-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
VS
GND
RSET
CPRSET VCP
PLL
REF
DISTRIBUTION
REF
REFIN
REFINB
N DIVIDER
FUNCTION
SYNCB,
RESETB
PDB
R DIVIDER
AD9511
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
PLL
SETTINGS
STATUS
CLK2
CLK1
CLK1B
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
LVPECL
/1, /2, /3... /31, /32
SCLK
SDIO
SDO
CSB
/1, /2, /3... /31, /32
SERIAL
CONTROL
PORT
/1, /2, /3... /31, /32
LVDS/CMOS
LVDS/CMOS
CLK2B
LVPECL
OUT0
OUT0B
OUT1
OUT1B
OUT2
OUT2B
OUT3
OUT3B
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
螖
T
DELAY
ADJUST
OUT4
OUT4B
05286-001
Figure 1.
GENERAL DESCRIPTION
The AD9511 provides a multi-output clock distribution
function along with an on-chip PLL core. The design
emphasizes low jitter and phase noise to maximize data
converter performance. Other applications with demanding
phase noise and jitter requirements also benefit from this part.
The PLL section consists of a programmable reference divider
(R); a low noise phase frequency detector (PFD); a precision
charge pump (CP); and a programmable feedback divider (N).
By connecting an external VCXO or VCO to the CLK2/CLK2B
pins, frequencies up to 1.6 GHz may be synchronized to the
input reference.
There are five independent clock outputs. Three outputs are
LVPECL (1.2 GHz), and two are selectable as either LVDS
(800 MHz) or CMOS (250 MHz) levels.
Each output has a programmable divider that may be bypassed
or set to divide by any integer up to 32. The phase of one clock
output relative to another clock output may be varied by means
of a divider phase select function that serves as a coarse timing
adjustment. One of the LVDS/CMOS outputs features a
programmable delay element with full-scale ranges up to 10 ns
of delay. This fine tuning delay block has 5-bit resolution, giving
32 possible delays from which to choose for each full-scale
setting.
The AD9511 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9511 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated by
connecting the charge pump supply (VCP) to 5.5 V. The
temperature range is 鈭?0掳C to +85掳C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
漏2005 Analog Devices, Inc. All rights reserved.

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