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AT49BV6416 Datasheet

  • AT49BV6416

  • 64-megabit (4M x 16) Page Mode 2.7-volt Flash Memory

  • 612.00KB

  • 31页

  • ATMEL

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Features
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64-megabit (4M x 16) Flash Memory
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2.7V - 3.6V Read/Write
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High Performance
鈥?Asynchronous Access Time 鈥?70 ns
鈥?Page Mode Read Time 鈥?20 ns
Sector Erase Architecture
鈥?Eight 4K Word Sectors with Individual Write Lockout
鈥?One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors 鈥?700 ms; 4K Word Sectors 鈥?200 ms
Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not Being
Programmed/Erased
鈥?Memory Plane A: 16M of Memory Including Eight 4K Word Sectors
鈥?Memory Plane B: 16M of Memory Consisting of 32K Word Sectors
鈥?Memory Plane C: 16M of Memory Consisting of 32K Word Sectors
鈥?Memory Plane D: 16M of Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
鈥?Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
鈥?Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
鈥?30 mA Active
鈥?35 碌A Standby
2.2V I/O Option Reduces Overall System Power
Data Polling and Toggle Bit for End of Program Detection
VPP Pin for Write Protection and Accelerated Program Operations
RESET Input for Device Initialization
TSOP Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
Green (Pb/Halide-free) Packaging Option
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64-megabit
(4M x 16)
Page Mode
2.7-volt Flash
Memory
AT49BV6416
AT49BV6416T
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1. Description
The AT49BV6416(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided
into multiple sectors and planes for erase operations. The device can be read or
reprogrammed off a single 2.7V power supply, making it ideally suited for in-system
programming. The output voltage can be separately controlled down to 2.2V through
the VCCQ supply pin. The device can operate in the asynchronous or page read
mode.
The AT49BV6416(T) is divided into four memory planes. A read operation can occur
in any of the three planes which is not being programmed or erased. This concurrent
operation allows improved system performance by not requiring the system to wait for
a program or erase operation to complete before a read is performed. To further
increase the flexibility of the device, it contains an Erase Suspend and Program Sus-
pend feature. This feature will put the erase or program on hold for any amount of time
and let the user read data from or program data to any of the remaining sectors. There
is no reason to suspend the erase or program operation if the data to be read is in
another memory plane. The end of program or erase is detected by Data Polling or
toggle bit.
3451C鈥揊LASH鈥?/05

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