鈥?/div>
Left-Justified, I虏S, TDM
8-channel TDM Interface Formats
Additional Control Port Features
!
Supports Standard I虏C or SPI Control Interface
!
Individual Channel HPF Disable
!
Overflow Detection for Individual Channels
!
Mute Control for Individual Channels
!
Independent Power-Down Control per Channel
!
Low Latency Digital Filter
!
Less than 600 mW Power Consumption
!
On-Chip Oscillator Driver
!
Operation as System Clock Master or Slave
!
Differential Analog Architecture
Pair
VA
5V
VD
3.3 - 5V
VLC
1.8 - 5V
Configuration
Registers
Control Interface
I
2
C,SPI
or Pins
Level
Translator
Internal
Oscillator
Device
Control
Voltage
Reference
8 Differential
Analog Inputs
Multi-Bit
鈭單?/div>
ADC
Decimation
Filter
High Pass
Filter
Serial
Audio Out
PCM or
TD
M
Level
Translator
Digital
Audio
VLS
1.8 - 5V
Advanced Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
漏
Cirrus Logic, Inc. 2005
(All Rights Reserved)
JULY '05
DS624A1
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