(CS5532/34) performance. The ADCs are optimized for
applications.
64脳. These ADCs also include a fourth order
鈭單?/div>
modu-
lator followed by a digital filter which provides twenty
selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30,
50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600,
1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt Trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.
ORDERING INFORMATION
See page 48
Delta-Sigma Analog-to-Digital Converter
Linearity Error: 0.0007% FS
Noise Free Resolution: Up to 23 bits
Two or Four Channel Differential MUX
Scalable Input Span via Calibration
卤5 mV to differential 卤2.5V
Scalable V
REF
Input: Up to Analog Supply
Simple three-wire serial interface
SPI and Microwire鈩?Compatible
Schmitt Trigger on Serial Clock (SCLK)
R/W Calibration Registers Per Channel
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
漏
庐
VA+
C1
C2
VREF+
VREF-
VD+
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
MUX
CS
PGIA
1,2,4,8,16
32,64
DIFFERENTIAL
4
TH
ORDER
鈭單?/div>
MODULATOR
PROGRAMMABLE
SINC FIR FILTER
SERIAL
INTERFACE
SDI
SDO
SCLK
(CS5533/34
SHOWN)
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
LATCH
VA-
A0/GUARD
A1
OSC1
OSC2
DGND
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
MAR 鈥?2
DS289PP5
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