CY2DL814SCT Datasheet

  • CY2DL814SCT

  • 1:4 Clock Fanout Buffer

  • 114.10KB

  • 8页

  • CYPRESS

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ComLink鈩?Series
CY2DL814
1:4 Clock Fanout Buffer
Features
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Low-voltage operation
V
DD
= 3.3V
1:4 Fanout
Single-input configurable for
鈥?LVDS, LVPECL, or LVTTL
鈥?Four differential pairs of LVDS outputs
Drives 50- or 100-ohm load (selectable)
Low input capacitance
Low output skew
Does not exceed Bellcore 802.3 standards
Operation at
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350 MHz 鈥?700 Mbps
Low propagation delay
Typical (tpd < 4 ns)
Industrial versions available
Packages available include TSSOP/SOIC
Description
The Cypress CY2 series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry鈥檚 fastest logic.
The Cypress CY2DL814 fanout buffer features a single
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS
output pairs.
Designed for data-communication clock management applica-
tions, the fanout from a single input reduces loading on the
input clock.
The CY2DL814 is ideal for both level translations from single
ended to LVDS and/or for the distribution of LVDS-based clock
signals. The Cypress CY2DL814 has configurable input and
output functions. The input can be selectable for
LVPECL/LVTTL or LVDS signals while the output driver鈥檚
support standard and high drive LVDS. Drive either a 50-ohm
or 100-ohm line with a single part number/device.
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Block Diagram
Pin Configuration
EN1
EN2
Q1A
Q1B
EN1
CONFIG
CNTRL
VDD
GND
IN+
IN-
EN2
Q3A
Q3B
IN+
IN-
LVDS /
LVPECL /
LVTTL
CONFIG
Q2A
Q2B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
16-pin TSSOP/SOIC
Q4A
Q4B
CNTRL
OUTPUT
LVDS
Cypress Semiconductor Corporation
Document #: 38-07057 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised December 14, 2002
CY2DL814

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