CY2DL814SCT Datasheet

  • CY2DL814SCT

  • 1:4 Clock Fanout Buffer

  • 114.10KB

  • 8页

  • CYPRESS

扫码查看芯片数据手册

上传产品规格书

PDF预览

ComLink鈩?Series
CY2DL814
Table 8. D.C Electrical Characteristics: 3.3V鈥揕VTTL/LVCMOS Input
Parameter
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
V
H
Parameter
I
V
OD
I
VOC(SS)
Delta
VOC(SS)
VOC(PP)
I
OS
Voh
Vol
Parameter
Rise Time
Description
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Input Hysteresis
Description
Steady-state common-mode
output voltage
Change in VOC(SS) between
logic states
Peak to peak common mode
output voltage
Output short circuit
Output voltage high
Output voltage low
Description
Conditions
RL = 100 ohm
QA = 0V or QB = 0V
RL = 100 ohm
925
鈥?0
3
Conditions
RL = 100 ohm
Conditions
Guaranteed Logic High Level
Guaranteed Logic Low Level
V
DD
= Max.
V
DD
= Max.
V
DD
= Max.,
V
IN
=
V
DD
(Max.)
V
DD
= Min.,
I
IN = 鈥?8 mA
鈥?.7
80
Min.
0.25
Typ.
Max.
0.45
226
50
150
鈥?0
1475
V
IN
= 2.7V
V
IN
= 0.5V
Min.
2
0.8
1
鈥?
20
鈥?.2
Typ.
Max.
Unit
V
V
碌A
碌A
碌A
V
mV
Unit
V
mV
mV
mV
mA
mV
mV
Table 9. D.C Electrical Characteristics: 3.3V鈥揕VDS OUTPUT
Differential output voltage p-p V
DD
= 3.3V, V
IN
= V
IH
, or V
IL
Table 10. AC Parameters
Min. Typ. Max. Unit
1.4
ns
Pin control (pin 3) logic is 鈥淔ALSE鈥?/div>
CL鈥?0 pF
defaulting to 100 ohm output drivers. RL and CL to G
ND
3 CL = C
intrinsic
and C
external
Differential 20% to 80%
Pin control (pin 3) logic is 鈥淭rue鈥?/div>
defaulting to 50 ohm output drivers.
Differential 20% to 80%
CL鈥?0 pF
RL and CL to G
ND
3 CL = C
intrinsic
and C
external
Fall Time
Rise Time
RL = 50 ohm
Output boost
350
1.4
600
ns
ps
Fall Time
Table 11. AC Switching Characteristics @ 3.3 V
(V
DD
= 3.3V 卤5%, Temperature = 鈥?0掳C to +85掳C)
Parameter
t
PLH
t
PHL
T
pd
T
Pe
T
pd
t
SK(0)
t
SK(p)
t
SK(t)
Description
Propagation Delay 鈥?Low to High
Propagation Delay 鈥?High to Low
Propagation Delay
Enable (EN) to functional operation
Functional operation to Disable
Output Skew: Skew between outputs of the same
package (in phase)
Pulse Skew: Skew between opposite transitions of the
same output (t
PHL
鈥搕
PLH
)
Package Skew: Skew between outputs of different
V
ID
= 100 mV
packages at the same power supply voltage, temper-
ature and package type. Same input signal level and
output load.
0.2
Conditions
V
OD
= 100 mV
Min.
3
3
3
350
Typ.
4
4
4
600
ps
Unit
ns
ns
ns
ns
ns
ns
ns
Max.
5
5
5
6
5
0.2
IN [+,-] to Q[A,B] Data and Clock Speed
IN [1,2] to Q[A,B] Control Speed
Q[A,B] Output Skews
1
ns
Document #: 38-07057 Rev. *A
Page 4 of 8

CY2DL814SCT相关型号PDF文件下载

扫码下载APP,
一键连接广大的电子世界。

在线人工客服

买家服务:
卖家服务:

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号,
第一时间获取资讯。

建议反馈

联系人:

联系方式:

按住滑块,拖拽到最右边
>>
感谢您向阿库提出的宝贵意见,您的参与是维库提升服务的动力!意见一经采纳,将有感恩红包奉上哦!