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CY7C09159AV

CY7C09169AV

3.3V 8K/16K x 9

Synchronous Dual Port Static RAM

Features

鈥?True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

鈥?Two Flow-Through/Pipelined devices

鈥?8K x 9 organization (CY7C09159AV)

鈥?16K x 9 organization (CY7C09169AV)

鈥?Three Modes

鈥?Flow-Through

鈥?Pipelined

鈥?Burst

鈥?Pipelined output mode on both ports allows fast 83-MHz

operation

鈥?0.35-micron CMOS for optimum speed/power

v

鈥?High-speed clock to data access 9 and 12 ns (max.)

鈥?3.3V Low operating power

鈥?Active = 135 mA (typical)

鈥?Standby = 10

碌A

(typical)

鈥?Fully synchronous interface for easier operation

鈥?Burst counters increment addresses internally

鈥?Shorten cycle times

鈥?Minimize bus noise

鈥?/div>

鈥?Supported in Flow-Through and Pipelined modes

Dual Chip Enables for easy depth expansion

Automatic power-down

Commercial and industrial temperature ranges

Available in 100-pin TQFP

Logic Block Diagram

R/W

L

OE

L

R/W

R

OE

R

CE

0L

CE

1L

1

0/1

1

0/1

0

CE

0R

CE

1R

FT/Pipe

L

I/O

0L

鈭扞/O

8L

0/1

1

0

1

0/1

FT/Pipe

R

I/O

0R

鈭扞/O

8R

9

I/O

Control

[1]

I/O

Control

13/14

[1]

A

0

鈭扐

12/13L

CLK

L

ADS

L

CNTEN

L

CNTRST

L

13/14

Counter/

Address

Register

Decode

True Dual-Ported

RAM Array

Counter/

Address

Register

Decode

A

0

鈭扐

12/13R

CLK

R

ADS

R

CNTEN

R

CNTRST

R

Notes:

1. A

0

鈭?/div>

A

12

for 8K; A

0

鈭?/div>

A

13

for 16K.

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation

鈥?3901 North First Street 鈥?San Jose 鈥?CA 95134 鈥?408-943-2600

Document #: 38-06053 Rev. **

Revised September 21, 2001

型号

版本

描述

厂商

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