鈥?/div>
鈥?Supported in Flow-Through and Pipelined modes
Dual Chip Enables for easy depth expansion
Upper and lower byte controls for bus matching
Automatic power-down
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
LB
R
OE
R
FT/Pipe
L
9
0/1
1b 0b 1a 0a
b
a
0a 1a 0b 1b
a
b
0/1
FT/Pipe
R
9
I/O
9L
鈥揑/O
17L
9
I/O
9R
鈥揑/O
17R
I/O
Control
I/O
Control
9
I/O
0L
鈥揑/O
8L
A
0L
鈥揂
11/12L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
[2]
I/O
0R
鈥揑/O
8R
12/13
12/13
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
A
0R
鈥揂
11/12R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
[2]
Notes:
1. See page 6 for Load Conditions.
2. A
0
鈥揂
11
for 4K; A
0
鈥揂
12
for 8K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
鈥?3901 North First Street 鈥?San Jose 鈥?CA 95134 鈥?408-943-2600
Document #: 38-06048 Rev. **
Revised September 19, 2001