Writing to the device is accomplished by taking Chip Enable
(CE1, CE2, CE3) active and Write Enable (WE) inputs LOW.
Data on the 24 I/O pins (I/O
0
through I/O
23
) is then written into
the location specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE1, CE2, CE3) active and Output Enable (OE) LOW
while forcing Write Enable (WE) HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The 24 input/output pins (I/O
0
through I/O
23
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE1, CE3 LOW, CE2 HIGH, and WE LOW).
The CY7C1024AV33 is available in a standard 119-ball BGA
package and a 100-pin TQFP package.
Functional Description
[1]
The CY7C1024AV33 is a high-performance CMOS static RAM
organized as 131,072 words by 24 bits. Easy memory expan-
sion is provided by an active LOW CE1, CE3, active HIGH
CE2, an active LOW Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.
Functional Block Diagram
V
CC
V
SS
A
0
ADDRESS BUFFER
ROW DECODER
DQ
0
MEMORY ARRAY
128K X 24
I/O BUFFER
DQ
23
A
16
COLUMN
DECODER
CONTROL
CE#
CE1#
CE2
WE#
OE#
Selection Guide
7C1024AV33-10
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
10
275
15
7C1024AV33-12
12
250
15
7C1024AV33-15
15
225
15
Note:
1. For guidelines on SRAM system design, please refer to the 鈥楽ystem Design Guidelines鈥?Cypress application note, available on the internet at www.cypress.com.
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