CY7C1303AV25 Datasheet

IC型号：
CY7C1303AV25
PDF描述：
18-Mb Burst of 2 Pipelined SRAM with QDR? Architecture
文件大小：
801.97KB
PDF页数：
20页
芯片厂家：
CYPRESS

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PRELIMINARY

CY7C1303AV25

CY7C1306AV25

18-Mb Burst of 2 Pipelined SRAM with

QDR鈩?Architecture

Features

鈥?Separate independent Read and Write data ports

鈥?Supports concurrent transactions

鈥?167-MHz Clock for high bandwidth

鈥?2.5 ns Clock-to-Valid access time

鈥?2-Word Burst on all accesses

鈥?Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 333 MHz) @167 MHz

鈥?Two input clocks (K and K) for precise DDR timing

鈥?SRAM uses rising edges only

鈥?Two output clocks (C and C) account for clock skew

and flight time mismatching

鈥?Single multiplexed address input bus latches address

inputs for both Read and Write ports

鈥?Separate Port Selects for depth expansion

鈥?Synchronous internally self-timed writes

鈥?2.5V core power supply with HSTL Inputs and Outputs

鈥?13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball

(11x15 matrix) Variable drive HSTL output buffers

鈥?Expanded HSTL output voltage (1.4V鈥?.9V)

鈥?JTAG Interface

鈥?Variable Impedance HSTL

Functional Description

The CY7C1303AV25 and CY7C1306AV25 are 2.5V

Synchronous Pipelined SRAMs equipped with QDR鈩?archi-

tecture. QDR architecture consists of two separate ports to

access the memory array. The Read port has dedicated Data

Outputs to support Read operations and the Write Port has

dedicated Data inputs to support Write operations. Access to

each port is accomplished through a common address bus.

The Read address is latched on the rising edge of the K clock

and the Write address is latched on the rising edge of K clock.

QDR has separate data inputs and data outputs to completely

eliminate the need to 鈥渢urn-around鈥?the data bus required with

common I/O devices. Accesses to the CY7C1303AV25/

CY7C1306AV25 Read and Write ports are completely

independent of one another. All accesses are initiated

synchronously on the rising edge of the positive input clock

(K). In order to maximize data throughput, both Read and

Write ports are equipped with Double Data Rate (DDR) inter-

faces. Therefore, data can be transferred into the device on

every rising edge of both input clocks (K and K) and out of the

device on every rising edge of the output clock (C and C, or K

and K when in single clock mode) thereby maximizing perfor-

mance while simplifying system design. Each address location

is associated with two 18-bit words (CY7C1303AV25) or two

36-bit words (CY7C1306AV25) that burst sequentially into or

out of the device.

Depth expansion is accomplished with a Port Select input for

each port. Each Port Selects allow each port to operate

independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1303AV25 鈥?1M x 18

CY7C1306AV25 鈥?512K x 36

Logic Block Diagram (CY7C1303AV25)

[17:0]

Write

Data Reg

Write Add. Decode

Write

Data Reg

Read Add. Decode

(18:0)

Address

CLK

Gen.

512Kx18

Memory

Array

512Kx18

Memory

Array

Address

(18:0)

Control

Logic

RPS

Read Data Reg.

Vref

WPS

BWS

Cypress Semiconductor Corporation

Document #: 38-05493 Rev. *A

鈥?/div>

3901 North First Street

鈥?/div>

Control

Logic

Reg.

Reg. 18

[17:0]

San Jose

CA 95134

鈥?/div>

408-943-2600

Revised June 1, 2004

CY7C1303AV25 PDF文件相关型号

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