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CY7C1305AV25-133BZC Datasheet

  • CY7C1305AV25-133BZC

  • 18-Mbit Burst of 4 Pipelined SRAM with QDR? Architecture

  • 804.00KB

  • 22页

  • CYPRESS

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PRELIMINARY
CY7C1305AV25
CY7C1307AV25
18-Mbit Burst of 4 Pipelined SRAM with
QDR鈩?Architecture
Features
鈥?Separate independent Read and Write data ports
鈥?Supports concurrent transactions
鈥?167-MHz clock for high bandwidth
鈥?2.5 ns Clock-to-Valid access time
鈥?4-Word Burst for reducing the address bus frequency
鈥?Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
鈥?Two input clocks (K and K) for precise DDR timing
鈥?SRAM uses rising edges only
鈥?Two output clocks (C and C) accounts for clock skew
and flight time mismatching
鈥?Single multiplexed address input bus latches address
inputs for both Read and Write ports
鈥?Separate Port Selects for depth expansion
鈥?Synchronous internally self-timed writes
鈥?2.5V core power supply with HSTL Inputs and Outputs
鈥?13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix)
鈥?Variable drive HSTL output buffers
鈥?Expanded HSTL output voltage (1.4V鈥?.9V)
鈥?JTAG interface
Functional Description
The CY7C1305AV25/CY7C1307AV25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to 鈥渢urn-around鈥?the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device鈥檚 Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305AV25) and four
36-bit words (CY7C1307AV25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying
system design by eliminating bus 鈥渢urn-arounds.鈥?/div>
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
鈥?CY7C1305AV25 鈥?1M x 18
鈥?CY7C1307AV25 鈥?512K x 36
Logic Block Diagram (CY7C1305AV25)
D
[17:0]
18
Write Write Write Write
Reg
Reg Reg Reg
Read Add. Decode
Write Add. Decode
A
[17:0]
Address
Register
18
Address
Register
256Kx18 Array
256Kx18 Array
256Kx18 Array
256Kx18 Array
18
A
(17:0)
K
K
CLK
Gen.
Control
Logic
RPS
C
C
Read Data Reg.
Vref
WPS
BWS
[0:1]
72
Control
Logic
36
36
Reg.
Reg.
18
Reg.
18
Q
[17:0]
Cypress Semiconductor Corporation
Document #: 38-05496 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 1, 2004

CY7C1305AV25-133BZC PDF文件相关型号

CY7C1305AV25-167BZC,CY7C1307AV25-100BZC,CY7C1307AV25-133BZC

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  • CY7C007
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  • CY7C017
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    32K x 8/9 Dual-Port Static RAM
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  • CY7C018
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    CY7C018
  • CY7C018
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
    CY7C018
  • CY7C019
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
    CY7C019
  • CY7C019
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
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  • CY7C024
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  • CY7C024
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  • CY7C025
    英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
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    CY7C025
  • CY7C026
    英文版
    16K x 16/18 Dual-Port Static RAM
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    CY7C026
  • CY7C027
    英文版
    32K/64K x 16/18 Dual-Port Static RAM
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    CY7C027
  • CY7C027
    英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
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  • CY7C028
    英文版
    32K/64K x 16/18 Dual-Port Static RAM
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    CY7C028
  • CY7C028
    英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
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