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CY7C136-15JC Datasheet

  • CY7C136-15JC

  • 2K x 8 Dual-Port Static RAM

  • 884.65KB

  • 19页

  • CYPRESS

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1CY 7C13 2/ CY7C1 36
fax id: 5201
CY7C132/CY7C136
CY7C142/CY7C146
2Kx8 Dual-Port Static RAM
Features
鈥?True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
鈥?2K x 8 organization
鈥?0.65-micron CMOS for optimum speed/power
鈥?High-speed access: 15 ns
鈥?Low operating power: I
CC
= 90 mA (max.)
鈥?Fully asynchronous operation
鈥?Automatic power-down
鈥?Master CY7C132/CY7C136 easily expands data bus
width to 16 or more bits using slave CY7C142/CY7C146
鈥?BUSY output flag on CY7C132/CY7C136; BUSY input
on CY7C142/CY7C146
鈥?INT flag for port-to-port communication (52-pin
PLCC/PQFP versions)
鈥?Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and
52-pin TQFP (CY7C136/146)
鈥?Pin-compatible and functionally equivalent to
IDT7132/IDT7142
Functional Description
The CY7C132/CY7C136/CY7C142 and CY7C146 are
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132/ CY7C136 can be utilized as either a
standalone 8-bit dual-port static RAM or as a MASTER du-
al-port RAM in conjunction with the CY7C142/CY7C146
SLAVE dual-port device in systems requiring 16-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. On the PLCC version, INT
is an interrupt flag indicating that data has been placed in a
unique location (7FF for the left port and 7FE for the right port).
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
The CY7C132/CY7C142 are available in 48-pin DIP. The
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
R/W
L
CE
L
OE
L
Pin Configuration
R/W
R
CE
R
OE
R
CE
L
R/W
L
BUSY
L
A
10L
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
DIP
Top View
1
2
3
4
5
6
7
8
9
10
11
12 7C132
13 7C142
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
CE
R
R/W
R
BUSY
R
A
10R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
C132-2
I/O
7L
I/O
0L
BUSY
L[1]
A
10L
A
0L
I/O
CONTROL
I/O
CONTROL
I/O
7R
I/O
0R
BUSY
R[1]
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
A
10R
A
0R
CE
L
OE
L
R/W
L
INT
L[2]
ARBITRA
TION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
CE
R
OE
R
R/W
R
INT
R[2]
C132-1
Notes:
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.
CY7C142/CY7C146 (Slave): BUSY is input.
2. Open drain outputs; pull-up resistor required.
Cypress Semiconductor Corporation
鈥?/div>
3901 North First Street
鈥?/div>
San Jose 鈥?/div>
CA 95134 鈥?/div>
408-943-2600
December 1989 鈥?Revised March 27, 1997

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