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SST34HF3244C Datasheet

  • SST34HF3244C

  • 32 Mbit Concurrent SuperFlash + 4/8 Mbit (P)SRAM ComboMemory

  • 524.00KB

  • 40页

  • SST

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32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory
SST34HF3244C
SST34HF32x4x32Mb CSF + 4/8/16 Mb SRAM (x16) MCP ComboMemory
Data Sheet
FEATURES:
鈥?Flash Organization: 2M x16 or 4M x8
鈥?Dual-Bank Architecture for Concurrent
Read/Write Operation
鈥?32 Mbit Top Sector Protection
鈥?8 Mbit + 24 Mbit
鈥?SRAM Organization:
鈥?4 Mbit: 256K x16
鈥?Single 2.7-3.3V Read and Write Operations
鈥?Superior Reliability
鈥?Endurance: 100,000 Cycles (typical)
鈥?Greater than 100 years Data Retention
鈥?Low Power Consumption:
鈥?Active Current: 25 mA (typical)
鈥?Standby Current: 20 碌A (typical)
鈥?Hardware Sector Protection (WP#)
鈥?Protects 8 KWord in the smaller bank by holding
WP# low and unprotects by holding WP# high
鈥?Hardware Reset Pin (RST#)
鈥?Resets the internal state machine to reading
data array
鈥?Byte Selection for Flash (CIOF pin)
鈥?Selects 8-bit or 16-bit mode
鈥?Sector-Erase Capability
鈥?Uniform 2 KWord sectors
鈥?Flash Chip-Erase Capability
鈥?Block-Erase Capability
鈥?Uniform 32 KWord blocks
鈥?Erase-Suspend / Erase-Resume Capabilities
鈥?Read Access Time
鈥?Flash: 70 ns
鈥?SRAM: 70 ns
鈥?Security ID Feature
鈥?SST: 128 bits
鈥?User: 256 Bytes
鈥?Latched Address and Data
鈥?Fast Erase and Program (typical):
鈥?Sector-Erase Time: 18 ms
鈥?Block-Erase Time: 18 ms
鈥?Chip-Erase Time: 35 ms
鈥?Program Time: 7 碌s
鈥?Automatic Write Timing
鈥?Internal
V
PP
Generation
鈥?End-of-Write Detection
鈥?Toggle Bit
鈥?Data# Polling
鈥?Ready/Busy# pin
鈥?CMOS I/O Compatibility
鈥?JEDEC Standard Command Set
鈥?Packages Available
鈥?56-ball LFBGA (8mm x 10mm)
鈥?62-ball LFBGA (8mm x 10mm)
鈥?All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST34HF3244C ComboMemory device integrates
either a 2M x16 or 4M x8 CMOS flash memory bank with a
256K x16 CMOS SRAM memory bank in a multi-chip
package (MCP). These devices are fabricated using SST鈥檚
proprietary, high-performance CMOS SuperFlash technol-
ogy incorporating the split-gate cell design and thick-oxide
tunneling injector to attain better reliability and manufactur-
ability compared with alternate approaches. The
SST34HF3244C are ideal for applications such as cellular
phones, GPS devices, PDAs, and other portable electronic
devices in a low power and small form factor system.
The SST34HF3244C feature dual flash memory bank
architecture allowing for concurrent operations between the
two flash memory banks and the SRAM. The devices can
read data from either bank while an Erase or Program
operation is in progress in the opposite bank. The two flash
memory banks are partitioned into 8 Mbit + 24 Mbit with top
sector protection options for storing boot code, program
code, configuration/parameter data and user data.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF3244C devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high-performance Program
operations, the flash memory banks provide a typical Pro-
gram time of 7 碌sec. The entire flash memory bank can be
erased and programmed word-by-word in typically 4 sec-
onds for the SST34HF3244C, when using interface fea-
tures such as Toggle Bit, Data# Polling, or RY/BY# to
indicate the completion of Program operation. To protect
漏2006 Silicon Storage Technology, Inc.
S71282-02-000
8/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.
CSF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

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