鈭?/div>
Q
8
O
E
=1
[14]
OE=0
Notes:
13. The clocks (RCLK, WCLK) can be free-running during reset.
14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
15. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the
programmable flag offset registers.
Document #: 38-06010 Rev. *A
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