CY7C4201V Datasheet

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CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Switching Waveforms

(continued)

First Data Word Latency after Reset with Simultaneous Read and Write

WCLK

t

DS

D

0

鈥揇

8

t

ENS

WEN1

WEN2

(if applicable)

t

SKEW1

RCLK

t

REF

EF

t

A

REN1,

REN2

[17]

D

0

(FIRSTVALID WRITE)

D

1

D

2

D

3

D

4

t

FRL

[16]

t

A

Q

0

鈥換

8

t

OLZ

t

OE

OE

D

0

D

1

Notes:

16. When t

SKEW1

> minimum specification, t

FRL

(maximum) = t

CLK

+ t

SKEW1

. When t

SKEW1

< minimum specification, t

FRL

(maximum) = either 2*t

CLK

+ t

SKEW1

or t

CLK

+ t

SKEW1

.

The Latency Timing applies only at the Empty Boundary (EF = LOW).

17. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06010 Rev. *A

Page 11 of 17

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