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CY7C4201V数据手册封面

CY7C4201V Datasheet

  • CY7C4201V

  • Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

  • 291.13KB

  • Cypress

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CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
64 x 9
8
6
0
8
256 x 9
7
Empty Offset (LSB) Reg.
Default Value = 007h
512 x 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
1K x 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
Empty Offset (LSB) Reg.
Default Value = 007h
8
0
8
0
8
0
(MSB)
0
8
1
(MSB)
00
0
8
6
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
0
8
0
8
0
(MSB)
0
8
1
(MSB)
00
0
2K x 9
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
4K x 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
8K x 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
2
(MSB)
000
0
8
3
(MSB)
0000
0
8
4
(MSB)
00000
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
2
(MSB)
000
0
8
3
(MSB)
0000
0
8
4
(MSB)
00000
0
Figure 1. Offset Register Location and Default Values
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as described
in
Table 1
or the default values are used, the programmable
Almost Empty Flag (PAE) and programmable Almost Full Flag
(PAF) states are determined by their corresponding offset
registers and the difference between the read and write
pointers.
Table 1. Writing the Offset Registers
LD
0
WEN
0
WCLK
[1]
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as
n
and determines the operation of PAE. PAE is synchro-
nized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK
when the FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as
m
and determines the operation of PAF. PAE is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4421V (64 鈥?m), CY7C4201V
(256 鈥?m), CY7C4211V (512 鈥?m), CY7C4221V (1K 鈥?m),
CY7C4231V (2K 鈥?m), CY7C4241V (4K 鈥?m), and
CY7C4251V (8K 鈥?m). PAF is set HIGH by the LOW-to-HIGH
transition of WCLK when the number of available memory
locations is greater than m.
0
1
1
1
0
1
Note:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06010 Rev. *A
Page 4 of 17

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CY7C4211V,CY7C4221V,CY7C4231V,CY7C4241V,CY7C4251V,CY7C4421V

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