ST72260G, ST72262G, ST72264G
Table 2. Hardware Register Map
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
to
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
MCC
SPI
WATCHDOG
ITC
ISPR0
ISPR1
ISPR2
ISPR3
MISCR1
SPIDR
SPICR
SPICSR
WDGCR
SICSR
MCCSR
PADR
PADDR
PAOR
Port B
PBDR
PBDDR
PBOR
Block
Register
Label
PCDR
PCDDR
PCOR
Register Name
Port C Data Register
Port C Data Direction Register
Port C Option Register
Reserved (1 Byte)
Port B Data Register
Port B Data Direction Register
Port B Option Register
Reserved (1 Byte)
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h
1)
00h
00h
R/W
R/W
R/W
00h
1)
00h
00h
R/W
R/W
R/W.
Reset
Status
Remarks
Port C
xx000000h
1)
R/W
2)
00h
R/W
2)
00h
R/W
2)
Port A
Reserved (17 Bytes)
Interrupt software priority register0
Interrupt software priority register1
Interrupt software priority register2
Interrupt software priority register3
Miscellanous register 1
SPI Data I/O Register
SPI Control Register
SPI Status Register
Watchdog Control Register
System Integrity Control / Status Register
Main Clock Control / Status Register
Reserved (1 Byte)
I
2
C Control Register
I
2
C Status Register 1
I
2
C Status Register 2
I
2
C Clock Control Register
I
2
C Own Address Register 1
I
2
C Own Address Register2
I
2
C Data Register
Reserved (2 Bytes)
00h
00h
00h
00h
00h
40h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
FFh
FFh
FFh
FFh
00h
xxh
0xh
00h
7Fh
000x 000x
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I
2
C
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