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ST72262G2数据手册封面

ST72262G2 Datasheet

  • ST72262G2

  • 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, ...

  • 2095.35KB

  • STMicroelectronics   STMicroelectronics

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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE
(Cont鈥檇)
11.4.8 Register Description
CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
7
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
0
SPR0
Bit 7 =
SPIE
Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF=1, MODF=1 or OVR=1
in the SPICSR register)
Bit 6 =
SPE
Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see
Section 11.4.5.1 "Master Mode Fault
(MODF)" on page 79).
The SPE bit is cleared by
reset, so the SPI peripheral is not initially connect-
ed to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 =
SPR2
Divider Enable.
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to
Table 16 SPI Master
mode SCK Frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note:
This bit has no effect in slave mode.
Bit 4 =
MSTR
Master Mode.
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see
Section 11.4.5.1 "Master Mode Fault
(MODF)" on page 79).
0: Slave mode
1: Master mode. The function of the SCK pin
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
Bit 3 =
CPOL
Clock Polarity.
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note:
If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 2 =
CPHA
Clock Phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture
edge.
1: The second clock transition is the first capture
edge.
Note:
The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 =
SPR[1:0]
Serial Clock Frequency.
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note:
These 2 bits have no effect in slave mode.
Table 16. SPI Master mode SCK Frequency
Serial Clock
f
CPU
/4
f
CPU
/8
f
CPU
/16
f
CPU
/32
f
CPU
/64
f
CPU
/128
SPR2
1
0
0
1
0
0
SPR1
0
0
0
1
1
1
SPR0
0
0
1
0
0
1
82/171

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