ST72262G2 Datasheet

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ST72260G, ST72262G, ST72264G

Table 5. Interrupt Mapping

N掳

Source

Block

RESET

TRAP

0

1

2

3

4

5

6

7

8

9

10

11

12

13

SCI

I

2

C

ei0

ei1

CSS

SPI

TIMER A

MCC

TIMER B

AVD

Reset

Software Interrupt

External Interrupt Port A7..0 (C5..0

1

)

External Interrupt Port B7..0 (C5..0 )

Clock Filter Interrupt

SPI Peripheral Interrupts

TIMER A Peripheral Interrupts

Time base interrupt

TIMER B Peripheral Interrupts

Auxiliary Voltage Detector interrupt

Not used

Not used

SCI Peripheral Interrupt

I

2

C Peripheral Interrupt

Not Used

Not Used

SCISR

I2CSRx

Lowest

Priority

no

no

CRSR

SPISR

TASR

MCCSR

TBSR

SICSR

1

Description

Register

Label

Priority

Order

Highest

Priority

Exit

from

HALT

yes

no

yes

no

yes

no

yes

no

Address

Vector

FFFEh-FFFFh

FFFCh-FFFDh

FFFAh-FFFBh

FFF8h-FFF9h

FFF6h-FFF7h

FFF4h-FFF5h

FFF2h-FFF3h

FFF0h-FFF1h

FFEEh-FFEFh

FFECh-FFEDh

FFEAh-FFEBh

FFE8h-FFE9h

FFE6h-FFE7h

FFE4h-FFE5h

FFE2h-FFE3h

FFE0h-FFE1h

N/A

Note 1.

Configurable by option byte.

Table 6. Nested Interrupts Register Map and Reset Values

Address

(Hex.)

Register

Label

7

SPI

001Ch

ISPR0

Reset Value

I1_3

1

AVD

001Dh

ISPR1

Reset Value

I1_7

1

I

2

C

001Eh

ISPR2

Reset Value

I1_11

1

I0_11

1

I1_10

1

I0_7

1

I0_3

1

I1_2

1

6

5

CSS

I0_2

1

I1_1

1

MCC

I1_5

1

I0_5

1

4

3

EI1

I0_1

1

I0_1

1

2

1

EI0

I0_0

1

0

TIMERB

I1_6

1

SCI

I0_10

1

I0_6

1

TIMERA

I1_4

1

I0_4

1

Not Used

I1_9

1

I0_9

1

Not Used

I1_8

1

I0_8

1

Not Used

001Fh

ISPR3

Reset Value

1

1

1

1

I1_13

1

I0_13

1

Not Used

I1_12

1

I0_12

1

32/171

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