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ST72262G2数据手册封面

ST72262G2 Datasheet

  • ST72262G2

  • 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, ...

  • 2095.35KB

  • STMicroelectronics   STMicroelectronics

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ST72260G, ST72262G, ST72264G
POWER SAVING MODES
(Cont鈥檇)
8.5 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
ST7 HALT instruction (see
Figure 27).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
Table 5, 鈥淚nterrupt
Mapping,鈥?on page 32)
or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see
Figure 26).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to 鈥?0b鈥?to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes immediately.
In the HALT mode the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the 鈥淲DGHALT鈥?op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 15.1 "OPTION BYTES" on page 157
for
more details).
Figure 26. HALT Mode Timing Overview
RUN
HALT
4096 CPU CYCLE
DELAY
RUN
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Figure 27. HALT Mode Flowchart
HALT
INSTRUCTION
ENABLE
WDGHALT
1)
1
WATCHDOG
RESET
OSCILLATOR
OFF
2)
PERIPHERALS OFF
CPU
OFF
0
I[1:0] BITS
0
WATCHDOG
DISABLE
N
RESET
N
INTERRUPT
Y
Y
3)
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
OFF
ON
1
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
ON
ON
ON
XX
4)
HALT
INSTRUCTION
RESET
OR
INTERRUPT
FETCH
VECTOR
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
Table 5, 鈥淚nterrupt Mapping,鈥?on page 32
for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0]
bits
in the CC reg-
ister are set during the interrupt routine and
cleared when the CC register is popped.
36/171

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