ST72260G, ST72262G, ST72264G
10 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.
10.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the ISxx bits of the Miscellaneous register and the
OPTION BYTE. This control allows you to have
two fully independent external interrupt source
sensitivities with configurable sources (using the
EXTIT option bit) as shown in
Figure 30
and
Fig-
ure 31.
Each external interrupt source can be generated
on four different events on the pin:
s
Falling edge
s
Rising edge
s
Falling and rising edge
s
Falling edge and low level
To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I[1:0] bits in the CC register are set to 1
(interrupt masked). See
Section 9.8 "I/O PORT
REGISTER DESCRIPTION" on page 43
and
Sec-
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page 46
for more details on the
programming.
PA0
PC5
Figure 30. Ext. Interrupt Sensitivity (EXTIT=0)
MISCR1
ei0
INTERRUPT
SOURCE
IS00
IS01
PA7
SENSITIVITY
CONTROL
PC0
MISCR1
ei1
INTERRUPT
SOURCE
IS10
IS11
PB7
SENSITIVITY
CONTROL
PB0
Figure 31. Ext. Interrupt Sensitivity (EXTIT=1)
MISCR1
ei0
INTERRUPT
SOURCE
IS00
IS01
PA7
SENSITIVITY
CONTROL
PA0
10.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscel-
laneous alternate functions:
s
Main clock signal (f
CPU
) output on PC2
s
SPI pin configuration:
鈥?SS pin internal control to use the PB7 I/O port
function while the SPI is active.
鈥?Master output capability on the MOSI pin
(PB4) deactivated while the SPI is active.
鈥?Slave output capability on the MISO pin (PB5)
deactivated while the SPI is active.
These functions are described in detail in the
Sec-
tion 10.3 "MISCELLANEOUS REGISTER DE-
SCRIPTION" on page 46.
PB7
ei1
INTERRUPT
SOURCE
MISCR1
IS10
IS11
PB0
PC5
SENSITIVITY
CONTROL
PC0
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