ST72260G, ST72262G, ST72264G
MISCELLANEOUS REGISTERS
(Cont鈥檇)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read /Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
MOD SOD
SSM
0
SSI
Caution:
This register has been provided for com-
patibility with the ST72254 family only. The same
bits are available in the SPICSR register. New ap-
plications must use the SPICSR register. Do not
use both registers, this will cause the SPI to mal-
function.
Bits 7:4 =
Reserved
always read as 0
Bits 3 =
MOD
SPI Master Output Disable
This bit is set and cleared by software. When set, it
disables the SPI Master (MOSI) output signal.
0: SPI Master Output enabled.
1: SPI Master Output disabled.
Bit 2 =
SOD
SPI Slave Output Disable
This bit is set and cleared by software. When set it
disable the SPI Slave (MISO) output signal.
0: SPI Slave Output enabled.
1: SPI Slave Output disabled.
Bit 1 =
SSM
SS mode selection
This bit is set and cleared by software.
0: Normal mode - the level of the SPI SS signal is
input from the external SS pin.
1: I/O mode, the level of the SPI SS signal is read
from the SSI bit.
Bit 0 =
SSI
SS internal mode
This bit replaces the SS pin of the SPI when the
SSM bit is set to 1. (see SPI description). It is set
and cleared by software.
Table 11. Miscellaneous Register Map and Reset Values
Address
(Hex.)
0020h
0040h
Register
Label
MISCR1
Reset Value
MISCR2
Reset Value
7
IS11
0
0
6
IS10
0
0
5
MCO
0
0
4
IS01
0
0
3
IS00
0
MOD
0
2
CP1
0
SOD
0
1
CP0
0
SSM
0
0
SMS
0
SSI
0
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