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ST72262G2数据手册封面

ST72262G2 Datasheet

  • ST72262G2

  • 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, ...

  • 2095.35KB

  • STMicroelectronics   STMicroelectronics

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ST72260G, ST72262G, ST72264G
MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK
(Cont鈥檇)
11.2.2 Low Power Modes
Bit 7:4 =
reserved
Mode
WAIT
Description
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.
No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with 鈥渆xit
from HALT鈥?capability.
Bit 3:2 =
TB[1:0]
Time base control
These bits select the programmable divider time
base. They are set and cleared by software.
Time Base
Counter
Prescaler f
OSC2
=4MHz f
OSC2
=8MHz
16000
32000
80000
200000
4ms
8ms
20ms
50ms
2ms
4ms
10ms
25ms
TB1
0
0
1
1
TB0
0
1
0
1
ACTIVE-
HALT
HALT
11.2.3 Interrupts
The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).
Interrupt Event
Time base overflow
event
Enable
Event
Control
Flag
Bit
OIF
OIE
Exit
from
Wait
Yes
Exit
from
Halt
No
1)
A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid an unwanted time shift. This allows to
use this time base as a real time clock.
Bit 1 =
OIE
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from ACTIVE-
HALT mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode
.
MAIN CLOCK CONTROLLER WITH REAL
TIME CLOCK (Cont鈥檇)
Bit 0 =
OIF
Oscillator interrupt flag
This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has reached the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION:
The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
Note:
The MCC/RTC interrupt wakes up the MCU from
ACTIVE-HALT mode, not from HALT mode.
11.2.4 Register Description
MCC CONTROL/STATUS REGISTER (MCCSR)
Read /Write
Reset Value: 0000 0000 (00h
)
7
0
0
0
0
TB1
TB0
OIE
0
OIF
Table 13. Main Clock Controller Register Map and Reset Values
Address
(Hex.)
0025h
0026h
Register
Label
SICSR
Reset Value
MCCSR
Reset Value
7
VDS
0
0
6
VDIE
0
0
5
VDF
0
0
4
LVDRF
x
0
3
2
CFIE
0
TB0
0
1
CSSD
0
OIE
0
0
WDGRF
x
OIF
0
0
TB1
0
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