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ST72262G2数据手册封面

ST72262G2 Datasheet

  • ST72262G2

  • 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, ...

  • 2095.35KB

  • STMicroelectronics   STMicroelectronics

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ST72260G, ST72262G, ST72264G
16-BIT TIMER
(Cont鈥檇)
Notes:
1. After a processor write cycle to the OCiHR reg-
ister, the output compare function is inhibited
until the OCiLR register is also written.
2. If the OCiE bit is not set, the OCMPi pin is a
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
3. When the timer clock is f
CPU
/2, OCFi and
OCMPi are set while the counter value equals
the OCiR register value (see
Figure 43 on page
63).
This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
CPU
/4, f
CPU
/8 or in
external clock mode, OCFi and OCMPi are set
while the counter value equals the OC
iR
regis-
ter value plus 1 (see
Figure 44 on page 63).
4. The output compare functions can be used both
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
5. The value in the 16-bit OC
i
R register and the
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
Figure 42. Output Compare Block Diagram
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
16-bit
OUTPUT COMPARE
CIRCUIT
(Control Register 2)
CR2
(Control Register 1)
CR1
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
Latch
1
OCMP1
Pin
OCMP2
Pin
16-bit
16-bit
OC1R
Register
OCF1
OCF2
0
0
0
Latch
2
OC2R
Register
(Status Register)
SR
62/171

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