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ST72262G2数据手册封面

ST72262G2 Datasheet

  • ST72262G2

  • 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, ...

  • 2095.35KB

  • STMicroelectronics   STMicroelectronics

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ST72260G, ST72262G, ST72264G
SERIAL PERIPHERAL INTERFACE
(Cont鈥檇)
11.4.5.4 Single Master and Multimaster
Configurations
There are two types of SPI systems:
鈥?Single Master System
鈥?Multimaster System
Single Master System
A typical single master system may be configured,
using a
device
as the master and four
device
s as
slaves (see
Figure 53).
The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.
The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.
Note:
To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.
For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written to its SPIDR
register.
Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.
Multi-Master System
A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.
The multi-master system is principally handled by
the MSTR bit in the SPICR register and the MODF
bit in the SPICSR register.
Figure 53. Single Master / Multiple Slave Configuration
SS
SCK
Slave
Device
MOSI MISO
SS
SCK
Slave
Device
MOSI MISO
SS
SCK
Slave
Device
MOSI MISO
SS
SCK
Slave
Device
MOSI MISO
MOSI MISO
SCK
Master
Device
5V
SS
Ports
80/171

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