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ST72262G2数据手册封面

ST72262G2 Datasheet

  • ST72262G2

  • 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, ...

  • 2095.35KB

  • STMicroelectronics   STMicroelectronics

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ST72260G, ST72262G, ST72264G
SERIAL COMMUNICATIONS INTERFACE
(Cont鈥檇)
CONTROL REGISTER 2 (SCICR2)
Notes:
Read/Write
鈥?During transmission, a 鈥?鈥?pulse on the TE bit
(鈥?鈥?followed by 鈥?鈥? sends a preamble (idle line)
Reset Value: 0000 0000 (00 h)
after the current word.
7
0
鈥?When TE is set there is a 1 bit-time delay before
the transmission starts.
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Caution:
The TDO pin is free for general purpose
I/O only when the TE and RE bits are both cleared
(or if TE is never set).
Bit 7 =
TIE
Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 2 =
RE
Receiver enable.
1: An SCI interrupt is generated whenever
This bit enables the receiver. It is set and cleared
TDRE=1 in the SCISR register
by software.
0: Receiver is disabled
Bit 6 = TCIE
Transmission complete interrupt ena-
1: Receiver is enabled and begins searching for a
ble
start bit
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 1 =
RWU
Receiver wake-up.
1: An SCI interrupt is generated whenever TC=1 in
This bit determines if the SCI is in mute mode or
the SCISR register
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
Bit 5 =
RIE
Receiver interrupt enable.
recognized.
This bit is set and cleared by software.
0: Receiver in Active mode
0: Interrupt is inhibited
1: Receiver in Mute mode
1: An SCI interrupt is generated whenever OR=1
Note:
Before selecting Mute mode (setting the
or RDRF=1 in the SCISR register
RWU bit), the SCI must receive some data first,
otherwise it cannot function in Mute mode with
Bit 4 =
ILIE
Idle line interrupt enable.
wakeup by idle line detection.
This bit is set and cleared by software.
0: Interrupt is inhibited
Bit 0 =
SBK
Send break.
1: An SCI interrupt is generated whenever IDLE=1
This bit set is used to send break characters. It is
in the SCISR register.
set and cleared by software.
Bit 3 =
TE
Transmitter enable.
This bit enables the transmitter. It is set and
cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
0: No break character is transmitted
1: Break characters are transmitted
Note:
If the SBK bit is set to 鈥?鈥?and then to 鈥?鈥? the
transmitter will send a BREAK word at the end of
the current word.
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