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ISL6529CB Datasheet

  • ISL6529CB

  • Dual Regulator–Synchronous Rectified Buck PWM and Linear Po...

  • 460.00KB

  • 19页

  • INTERSIL   INTERSIL

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ISL6529, ISL6529A
interval required to slew the inductor current from an initial
current value to the final current level. During this interval the
difference between the inductor current and the load current
must be supplied by the output capacitor(s). Minimizing the
response time can minimize the output capacitance
required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L
O
脳
I
TRAN
-
t
RISE
= -------------------------------
V
IN
鈥?/div>
V
OUT
L
O
脳
I
TRAN
t
FALL
= ------------------------------
-
V
OUT
TRANSISTOR SELECTION/CONSIDERATIONS
The ISL6529, ISL6529A require three external transistors.
One N-Channel MOSFET is used as the upper switch in a
standard buck topology PWM converter. Another MOSFET
is used as the lower synchronous switch. The linear
controller drives the gate of an N-Channel MOS transistor
used as the series pass element. The chosen MOSFET
r
DS(ON)
determines the maximum drop out voltage of the
regulator. For all practical purposes, the MOSFET appears
as a variable resistor. All he MOSFET transistors should be
selected based upon r
DS(ON)
, gate supply requirements,
and thermal management considerations.
(EQ. 13)
Upper MOSFET SWITCH Selection
(EQ. 14)
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses account for a large portion of the power
dissipation of the upper MOSFET. Switching losses also
contribute to the overall MOSFET power loss.
2
P
ConductionUpper
鈮?/div>
I
o
脳
r
DS
(
on
)
脳
D
where I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load.
With a +3.3V input source, the worst case response time can
be either at the application or removal of load and dependent
upon the output voltage setting. Be sure to check both of
these equations at the minimum and maximum output levels
for the worst case response time.
(EQ. 15)
1
-
P
Switching
鈮?/div>
-- I
o
脳
V
IN
脳
t
SW
脳
F
SW
2
(EQ. 16)
Input Capacitor Selection
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.
Use a mix of input bypass capacitors to control the voltage
overshoot across the switching MOSFETs. Use ceramic
capacitance for the high frequency decoupling and bulk
capacitors to supply the RMS current. Small ceramic
capacitors can be placed very close to the upper MOSFET
to suppress the voltage induced in the parasitic circuit
impedances. Connect them directly to ground with a via
placed very close to the ceramic capacitor footprint.
For a through-hole design, several aluminum electrolytic
capacitors may be needed. For surface mount designs,
tantalum or special polymer capacitors can be used, but
caution must be exercised with regard to the capacitor surge
current rating. These capacitors must be capable of handling
the surge-current at power-up.
where I
o
is the maximum load current, D is the duty cycle of
the converter (defined as V
O
/V
IN
), t
SW
is the switching
interval, and F
SW
is the PWM switching frequency.
The lower MOSFET has only conduction losses since it
switches with zero voltage across the device. Conduction
loss is:
2
P
ConductionLower
鈮?/div>
I
o
脳
r
DS
(
on
)
脳 (
1
鈥?/div>
D
)
(EQ. 17)
These equations assume linear voltage-current transitions
and are approximations. The gate-charge losses are
dissipated by the ISL6529 and do not heat the MOSFET.
However, large gate-charge increases the switching interval,
t
SW
, which increases the upper MOSFET switching losses.
Ensure that the MOSFET is within its maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature, air flow, and load current requirements.
The gate drive to the switching transistors ranges from
slightly below 12V to ground. Because of the large voltage
swing, logic-level transistors are not necessary in this
application.
16
FN9070.5
April 12, 2005

ISL6529CB 产品属性

  • 50

  • 集成电路 (IC)

  • PMIC - 稳压器 - 线性 + 切换式

  • -

  • 降压（降压）同步（1），线性（LDO）（1）

  • 任何功能

  • 2

  • 600kHz

  • 0.8 V ~ 3.3 V，15A

  • 0.8 V ~ 3.3 V，4A

  • -

  • 无

  • 无

  • 无

  • 3.3V，5V

  • 0°C ~ 70°C

  • 表面贴装

  • 14-SOIC（0.154"，3.90mm 宽）

  • 14-SOICN

  • -

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