您的位置：维库电子市场网 > Datasheet > CY7C64713

CY7C64713 Datasheet

  • CY7C64713

  • EZ-USB FX1? USB Microcontroller Full-speed USB Peripheral Co...

  • 424.00KB

  • 0页

  • CYPRESS

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

CY7C64713
The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK.
[16]
Table 23. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
Parameter
t
IFCLK
t
SPE
t
PEH
t
XFLG
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
Description
Min
20.83
8.6
2.5
13.5
Max
200
Unit
ns
ns
ns
ns
There is no specific timing requirement that needs to be met for
asserting the PKTEND pin concerning asserting SLWR.
PKTEND is asserted with the last data value clocked into the
FIFOs or thereafter. The only consideration is that the set up time
t
SPE
and the hold time t
PEH
for PKTEND must be met.
Although there are no specific timing requirements for asserting
PKTEND in relation to SLWR, there exists a specific case
condition that needs attention. When using the PKTEND to
commit a one byte or word packet, an additional timing
requirement must be met when the FIFO is configured to operate
in auto mode and it is necessary to send two packets back to
back:
鈻?/div>
In this particular scenario, the developer must assert the
PKTEND at least one clock cycle after the rising edge that
caused the last byte or word to be clocked into the previous auto
committed packet.
Figure 24
shows this scenario. X is the value
the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 24
shows a scenario where two packets are being
committed. The first packet is committed automatically when the
number of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte or word short packet being
committed manually using PKTEND. Note that there is at least
one IFCLK cycle timing between asserting PKTEND and
clocking of the last byte of the previous packet (causing the
packet to be committed automatically). Failing to adhere to this
timing results in the FX2 failing to send the one byte or word short
packet.
A full packet (defined as the number of bytes in the FIFO
meeting the level set in the AUTOINLEN register) committed
automatically followed by
A short one byte or word packet committed manually using the
PKTEND pin.
鈻?/div>
Figure 24. Slave FIFO Synchronous Write Sequence and Timing Diagram
t
IFCLK
IFCLK
t
SFA
t
FAH
FIFOADR
>= t
SWR
>= t
WRH
SLWR
t
SFD
t
FDH
t
SFD
X-3
t
FDH
t
SFD
X-2
t
FDH
t
SFD
X-1
t
FDH
t
SFD
X
t
FDH
t
SFD
1
t
FDH
DATA
X-4
At least one IFCLK cycle
t
SPE
t
PEH
PKTEND
Document #: 38-08039 Rev. *E
Page 41 of 54
[+] Feedback

CY7C64713 PDF文件相关型号

CY7C64713-100AXC,CY7C64714-56LFXC,CY7C65113-SC,CY7C65630-56LFXC

CY7C64713相关型号PDF文件下载

  • 型号
    版本
    描述
    厂商
    下载
  • CY7C006
    英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
    CY7C006
  • CY7C007
    英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
    CY7C007
  • CY7C008
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
    CY7C008
  • CY7C008
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
    CY7C008
  • CY7C009
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
    CY7C009
  • CY7C009
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
    CY7C009
  • CY7C016
    英文版
    16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
    Cypress
    CY7C016
  • CY7C017
    英文版
    32K x 8/9 Dual-Port Static RAM
    Cypress
    CY7C017
  • CY7C018
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
    CY7C018
  • CY7C018
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
    CY7C018
  • CY7C019
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS
    CY7C019
  • CY7C019
    英文版
    64K/128K x 8/9 Dual-Port Static RAM
    CYPRESS [C...
    CY7C019
  • CY7C024
    英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS
    CY7C024
  • CY7C024
    英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT...
    CYPRESS [C...
    CY7C024
  • CY7C025
    英文版
    4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int...
    Cypress
    CY7C025
  • CY7C026
    英文版
    16K x 16/18 Dual-Port Static RAM
    Cypress
    CY7C026
  • CY7C027
    英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
    CY7C027
  • CY7C027
    英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
    CY7C027
  • CY7C028
    英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS
    CY7C028
  • CY7C028
    英文版
    32K/64K x 16/18 Dual-Port Static RAM
    CYPRESS [C...
    CY7C028

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！