CY7C64713
Slave FIFO Synchronous Address
Figure 28. Slave FIFO Synchronous Address Timing Diagram
IFCLK
SLCS/FIFOADR [1:0]
t
SFA
t
FAH
The following table provides the Slave FIFO Synchronous Address Parameters.
[16]
Table 27. Slave FIFO Synchronous Address Parameters
Parameter
t
IFCLK
t
SFA
t
FAH
Description
Interface Clock Period
FIFOADR[1:0] to Clock Setup Time
Clock to FIFOADR[1:0] Hold Time
Min
20.83
25
10
Max
200
Unit
ns
ns
ns
Slave FIFO Asynchronous Address
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 29. Slave FIFO Asynchronous Address Timing Diagram
SLCS/FIFOADR [1:0]
t
SFA
RD/WR/PKTEND
t
FAH
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz
.
Table 28. Slave FIFO Asynchronous Address Parameters
Parameter
t
SFA
t
FAH
Description
FIFOADR[1:0] to RD/WR/PKTEND Setup Time
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
Min
10
10
Unit
ns
ns
Document #: 38-08039 Rev. *E
Page 43 of 54
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