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CY7C64713 Datasheet

  • CY7C64713

  • EZ-USB FX1? USB Microcontroller Full-speed USB Peripheral Co...

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CY7C64713
Although there are no specific timing requirement for asserting
PKTEND, there is a specific corner case condition that needs
attention while using the PKTEND to commit a one byte or word
packet. Additional timing requirements exist when the FIFO is
configured to operate in auto mode and it is necessary to send
two packets: a full packet (full defined as the number of bytes in
the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte or word
Sequence Diagram of a Single and Burst Asynchronous Read
packet committed manually using the PKTEND pin. In this case,
the external master must make sure to assert the PKTEND pin
at least one clock cycle after the rising edge that caused the last
byte or word to be clocked into the previous auto committed
packet (the packet with the number of bytes equal to what is set
in the AUTOINLEN register). Refer to
Table 20
on page 39 for
further details on this timing.
Figure 33. Slave FIFO Asynchronous Read Sequence and Timing Diagram
t
SFA
t
FAH
t
SFA
t
FAH
FIFOADR
t=0
t
RDpwl
t
RDpwh
T=0
t
RDpwl
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
RDpwh
SLRD
t=2
t=3
T=2
T=3
T=4
T=5
T=6
SLCS
t
XFLG
t
XFLG
FLAGS
t
XFD
t
XFD
N
t
OEoff
t
OEon
N+1
t
XFD
N+2
t
XFD
N+3
t
OEoff
DATA
Data (X)
Driven
t
OEon
N
SLOE
t=1
t=4
T=1
T=7
Figure 34. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLOE
SLRD
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLRD
SLOE
FIFO POINTER
N
N
Driven: X
N
N
N+1
N
N+1
Not Driven
N+1
N
N+1
N+1
N+2
N+1
N+2
N+2
N+3
N+2
N+3
Not Driven
FIFO DATA BUS
Not Driven
Figure 33
shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
鈻?/div>
鈻?/div>
鈻?/div>
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of t
RDpwl
and minimum de-active pulse width of
t
RDpwh
. If SLCS is used then, SLCS must be in asserted with
SLRD or before SLRD is asserted (that is, the SLCS and SLRD
signals must both be asserted to start a valid read condition).
The data that drives after asserting SLRD, is the updated data
from the FIFO. This data is valid after a propagation delay of
t
XFD
from the activating edge of SLRD. In
Figure 33,
data N is
the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is, SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note
In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After the SLRD
is asserted, the data from the FIFO is driven on the data bus
(SLOE must also be asserted) and then the FIFO pointer is incre-
mented.
鈻?/div>
Document #: 38-08039 Rev. *E
Page 46 of 54
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