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CY7C64713 Datasheet

  • CY7C64713

  • EZ-USB FX1? USB Microcontroller Full-speed USB Peripheral Co...

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CY7C64713
Sequence Diagram of a Single and Burst Asynchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
Figure 35. Slave FIFO Asynchronous Write Sequence and Timing Diagram
t
SFA
t
FAH
t
SFA
t
FAH
FIFOADR
t=0
t
WRpwl
t
WRpwh
T=0
t
WRpwl
t
WRpwh
t
WRpwl
t
WRpwh
t
WRpwl
t
WRpwh
SLWR
t =1
t=3
T=1
T=3
T=4
T=6
T=7
T=9
SLCS
t
XFLG
t
XFLG
FLAGS
t
SFD
t
FDH
t
SFD
t
FDH
N+1
T=2
T=5
t
SFD
t
FDH
N+2
t
SFD
t
FDH
N+3
T=8
DATA
t=2
N
t
PEpwl
t
PEpwh
PKTEND
Figure 35
shows the timing relationship of the SLAVE FIFO write
in an asynchronous mode. This diagram shows a single write
followed by a burst write of 3 bytes and committing the
4-byte-short packet using PKTEND.
鈻?/div>
The FIFO flag is also updated after t
XFLG
from the deasserting
edge of SLWR.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note
In the burst write mode, after SLWR is deasserted, the data
is written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incre-
mented.
In
Figure 35,
after the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet is committed to the
host using the PKTEND. The external device must be designed
to not assert SLWR and the PKTEND signal at the same time. It
must be designed to assert the PKTEND after SLWR is
deasserted and has met the minimum deasserted pulse width.
The FIFOADDR lines are to be held constant during the
PKTEND assertion.
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of t
SFA
. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of t
WRpwl
and minimum de-active pulse width of
t
WRpwh
. If the SLCS is used, it must be in asserted with SLWR
or before SLWR is asserted.
At t = 2, data must be present on the bus t
SFD
before the
deasserting edge of SLWR.
At t = 3, deasserting SLWR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
鈻?/div>
鈻?/div>
鈻?/div>
Document #: 38-08039 Rev. *E
Page 47 of 54
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