Load address on the rising edge of K clock; input write
data on K and K rising edges.
Read Cycle:
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
K
L-H
RPS
X
WPS
L
CY7C1303AV25
CY7C1306AV25
DQ
D(A+0) at
K(t)
鈫?/div>
Q(A+0) at
C(t+1)鈫?/div>
D=X
Q = High-Z
Previous
State
DQ
D(A+1) at
K(t)
鈫?/div>
Q(A+1) at
C(t+1)
鈫?/div>
D=X
Q = High-Z
Previous
State
L-H
L
X
L-H
Stopped
H
X
H
X
Write Descriptions (CY7C1303AV25)
[2, 8]
BWS
0
L
L
L
L
H
H
H
H
BWS
1
L
L
H
H
L
L
H
H
K
L-H
-
L-H
-
L-H
-
L-H
-
K
-
L-H
-
L-H
-
L-H
-
L-H
Comments
During the Data portion of a Write sequence, both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence, both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written into the
device. D
[17:9]
remains unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
) is written into the
device. D
[17:9]
remains unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into the device.
D
[8:0]
remains unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is written into the device.
D
[8:0]
remains unaltered.
No data is written into the device during this portion of a write operation.
No data is written into the device during this portion of a write operation.
Write Descriptions (CY7C1306AV25)
[2, 8]
BWS
0
L
L
L
L
H
H
H
BWS
1
L
L
H
H
L
L
H
BWS
2
L
L
H
H
H
H
L
BWS
3
L
L
H
H
H
H
H
K
L-H
-
L-H
-
L-H
-
L-H
K
-
L-H
-
L-H
-
L-H
-
Comments
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, all four bytes (D
[35:0]
) are
written into the device.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
)
is written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the lower byte (D
[8:0]
)
is written into the device. D
[35:9]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[17:9]
) is
written into the device. D
[8:0]
and D
[35:18]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
Notes:
2. X = Don't Care, H = Logic HIGH, L = Logic LOW,
鈫憆epresents
rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. 鈥淎鈥?represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. 鈥渢鈥?represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the 鈥渢鈥?clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
0
, BWS
1
, in the case of CY7C1303AV25 and also BWS
2
and BWS
3
in the case of CY7C1306AV25 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
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