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CY7C1303AV25 Datasheet

  • CY7C1303AV25

  • 18-Mb Burst of 2 Pipelined SRAM with QDR? Architecture

  • 801.97KB

  • 20页

  • CYPRESS

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PRELIMINARY
Write Descriptions (CY7C1306AV25)
[2, 8]
BWS
0
H
H
H
H
H
BWS
1
H
H
H
H
H
BWS
2
L
H
H
H
H
BWS
3
H
L
L
H
H
K
-
L-H
-
L-H
-
K
L-H
-
L-H
-
L-H
Comments
CY7C1303AV25
CY7C1306AV25
During the Data portion of a Write sequence, only the byte (D
[26:18]
) is
written into the device. D
[17:0]
and D
[35:27]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
During the Data portion of a Write sequence, only the byte (D
[35:27]
) is
written into the device. D
[26:0]
will remain unaltered.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
Document #: 38-05493 Rev. *A
Page 7 of 19

CY7C1303AV25 PDF文件相关型号

CY7C1303AV25-100BZC,CY7C1303AV25-133BZC,CY7C1303AV25-167BZC,CY7C1306AV25,CY7C1306AV25-133BZC

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