鈮?/div>
V
IL
f = f
MAX
=
100 MHz
1/t
CYC,
Inputs Static
Test Conditions
AC Input Requirements
Parameter
V
IH
V
IL
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Thermal Resistance
[16]
Parameter
螛
JA
螛
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51.
165 FBGA Package
16.7
6.5
Unit
掳C/W
掳C/W
Notes:
9. Power-up: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
10. All Voltage referenced to Ground.
11. Output are impedance controlled. I
OH
= 鈥揤
DDQ
/2)/(RQ/5) for values of 175鈩?<= RQ <= 350鈩?
12. Output are impedance controlled. I
OL
= (V
DDQ
/2)/(RQ/5) for values of 175鈩?<= RQ <= 350鈩?
13. Overshoot: V
IH
(AC) < V
DDQ
+0.85V (Pulse width less than t
CYC
/2), Undershoot: V
IL
(AC) > 鈥?.5V (Pulse width less than t
CYC
/2).
14. This spec is for all inputs except C and C Clock. For C and C Clock, V
IL
(Max.) = V
REF
鈥?0.2V.
15. V
REF
(Min.) = 0.68V or 0.46V
DDQ
, whichever is larger, V
REF
(Max.) = 0.95V or 0.54V
DDQ
, whichever is smaller.
16. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05493 Rev. *A
Page 8 of 19