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CY7C09349A-12AC Datasheet

  • CY7C09349A-12AC

  • 4K/8K x 18 Synchronous Dual-Port Static RAM

  • 640.00KB

  • 18页

  • CYPRESS

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CY7C09349A
CY7C09359A
Functional Description
The CY7C09349A and CY7C09359A are high-speed synchro-
nous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports
are provided, permitting independent, simultaneous access
for reads and writes to any location in memory.
[3]
Registers on
control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid t
CD2
= 6.5 ns
[1]
(pipe-
lined). Flow-through mode can also be used to bypass the
pipelined output register to eliminate access latency. In flow-
through mode data will be available t
CD1
= 15 ns after the
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address regis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH transition of the clock signal. The internal write pulse
is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
0
LOW and CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port鈥檚 burst counter is loaded with the port鈥檚 Address Strobe
(ADS). When the port鈥檚 Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port鈥檚 clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
3. When simultaneously writing to the same location, final value cannot be determined.
Document #: 38-06048 Rev. **
Page 2 of 17

CY7C09349A-12AC PDF文件相关型号

CY7C09359A-6AC,CY7C09359A-7AC

CY7C09349A-12AC 产品属性

  • 90

  • 集成电路 (IC)

  • 存储器

  • -

  • RAM

  • SRAM - 双端口，同步

  • 72K（4K x 18）

  • 12ns

  • 并联

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 100-LQFP

  • 100-TQFP（14x14）

  • 托盘

  • 428-1446

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