CY7C09349A
CY7C09359A
Pin Configuration
100-Pin TQFP (Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
[3] A12L
NC
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
VCC
FT/PIPEL
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
75
74
73
72
71
70
69
68
67
66
A8R
A9R
A10R
A11R
[3]
A12R
NC
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
OER
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
CY7C09359A (8K x 18)
CY7C09349A (4K x 18)
A7R
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/10R
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
Selection Guide
CY7C09349A
CY7C09359A
-6
[1]
f
MAX2
(MHz) (Pipelined)
Max. Access Time (ns) (Clock to Data, Pipelined)
Typical Operating Current I
CC
(mA)
Typical Standby Current for I
SB1
(mA)
(Both Ports TTL Level)
Typical Standby Current for I
SB3
(mA)
(Both Ports CMOS Level)
Note:
4. This pin is NC for CY7C09349A.
CY7C09349A
CY7C09359A
-7
83
7.5
235
40
0.05
CY7C09349A
CY7C09359A
-9
67
9
215
35
0.05
I/O9R
I/01R
VCC
GND
GND
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
VCC
CY7C09349A
CY7C09359A
-12
50
12
195
30
0.05
100
6.5
250
45
0.05
Document #: 38-06048 Rev. **
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