CS5381
LRCK output
tmslr
LRCK input
t slrd
SCLK output
t sdo
SCLK input
t sclkh
t stp t hld
t sclkl
SDOUT
MSB
MSB-1
MSB-2
MSB-3
SDOUT
MSB
MSB-1
Figure 13. Master Mode, Left-Justified SAI
Figure 14. Slave Mode, Left-Justified SAI
LRCK output
tmslr
LRCK input
t slrd
SCLK output
t sdo
SCLK input
t sclkh
t sclkl
t stp t hld
SDOUT
MSB
MSB-1
MSB-2 MSB-3
SDOUT
MSB
Figure 15. Master Mode, I虏S SAI
Figure 16. Slave Mode, I虏S SAI
LRCK
t setup
OVFL
t hold
Figure 17. OVFL Output Timing
DS563F2
11