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CS5342 Datasheet

  • CS5342

  • 105 dB, 192 kHz, MULTI-BIT AUDIO A/D CONVERTER

  • 739.07KB

  • 23页

  • CIRRUS

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CS5342
4.2.1
Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from
the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 18.
梅 256
梅 128
梅 64
梅 1.5
MCLK
梅3
1
梅4
Auto-Select
梅2
梅1
0
Single
Speed
Double
Speed
Quad
Speed
00
01
10
LRCK Output
(Equal to Fs)
M[1:0]
Single
Speed
Double
Speed
Quad
Speed
00
01
10
SCLK Output
Figure 18. CS5342 Master Mode Clocking
4.2.2
Operation as a Clock Slave
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock
be synchronously derived from the master clock and equal to 48x Fs or 64x Fs in Single-Speed Mode. In Double-
Speed and Quad-Speed Modes the serial clock must be derived synchronously from the master clock and equal to
48x Fs. Additionally, Quad-Speed Slave Mode is only specified for operation with a VA and VD at 5 V,
卤5%.
A unique feature of the CS5342 is the automatic selection of either Single, Double or Quad speed mode when op-
erating as a clock slave. The auto-mode select feature negates the need to configure the Mode pins to correspond
to the desired mode. The auto-mode selection feature supports all standard audio sample rates from 2 to 200 kHz.
However, there are ranges of non-standard audio sample rates that are not supported when operating with a fast
MCLK (768x, 384x, and 192x for Single, Double, and Quad Speed Modes respectively). Please refer to Table 1 on
page 15 for supported sample rate ranges.
16
DS608PP2

CS5342 PDF文件相关型号

CS5342-CZZ,CS5342-DZZ

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