-Replace MCLK low/high timing specifications with duty cycle specification.
-Redefine slave mode timing specifications under 鈥淪witching Characteristics.鈥?/div>
-Add requirement of SCLK/LRCK = 48x in Double and Quad Speed Modes.
-Increase minimum VL specification from 1.7 V to 2.38 V.
-Specify VA and VD at 5 V,
卤5%
for Quad-Speed Slave Mode.
-Reduce gain error specification under Analog Characteristics.
-Improve minimum and maximum specifications for full-scale input voltage.
-Initial Preliminary Release.
Update to include lead-free device ordering information.
Table 5. Revision History
Release
A1
A2
PP1
PP2
Aug 2004
22
DS608PP2