鈥?/div>
0
MUX
1
To TMR0 (Figure 6-6)
PSA
WDT
Time-out
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 9-9:
Address
2007h
81h
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Con铿乬. bits
OPTION
Bit 7
---
RBPU
Bit 6
BOREN
INTEDG
Bit 5
CP1
T0CS
Bit 4
CP0
T0SE
Bit 3
PWRTE
PSA
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note:
= Unimplemented location, read as 鈥?鈥?/div>
+ = Reserved for future use
_
DS30235G-page 58
Preliminary
漏
1998 Microchip Technology Inc.
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