ADSP-2185
TIMING PARAMETERS
Parameter
Clock Signals and Reset
Timing Requirements:
t
CKI
CLKIN Period
t
CKIL
CLKIN Width Low
t
CKIH
CLKIN Width High
Switching Characteristics:
t
CKL
CLKOUT Width Low
t
CKH
CLKOUT Width High
t
CKOH
CLKIN High to CLKOUT High
Control Signals
Timing Requirements:
RESET
Width Low
1
t
RSP
t
MS
Mode Setup Before
RESET
High
t
MH
Mode Setup After
RESET
High
5 t
CK
2
5
ns
ns
ns
60
20
20
0.5 t
CK
鈥?7
0.5 t
CK
鈥?7
0
150
ns
ns
ns
ns
ns
ns
Min
Max
Unit
20
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
t
CKI
t
CKIH
CLKIN
t
CKIL
t
CKCH
t
CKH
CLKOUT
t
CKL
PF(2:0)
*
t
MS
RESET
t
MH
*
PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 14. Clock Signals
REV. 0
鈥?7鈥?/div>
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